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freescale semiconductor data sheet: advance information document number: MPC5606E rev. 3, 08/2014 ? 2014 freescale semiconductor, inc. this document contains information on a product under development. freescale reserves the right to change or disc ontinue this product without notice. MPC5606E 121 mapbga 8 mm x 8mm note for bcm89810 document please refer to broadcom website and download the document ? single issue, 32-bit cpu core complex (e200z0h) ? compliant with power architecture ? embedded category ? variable length encoding (vle) only ?memory ? 512 kb on-chip code flash with ecc and erase/program controller ? additional 64 (4 16) kb on-chip data flash with ecc for eeprom emulation ? 96 kb on-chip sram with ecc ? fail-safe protection ? programmable watchdog timer ? non-maskable interrupt ? fault collection unit ? interrupts and events ? 16-channel edma controller ? 16 priority level controller ? up to 22 external interrupts ? pit implements four 32-bit timers ? 120 interrupts are routed via intc ? general purpose i/os ? individually programmable as input, output or special function ? 39 ? 1 general purpose etimer unit ? 6 timers each with up/down capabilities ? 16-bit resolution, cascadeable counters ? quadrature decode with rotation direction flag ? double buffer input capture and output compare ? communications interfaces ? 2 linflex channels (1 master/slave, 1 master only) ? 3 dspi controllers with automatic chip select generation (up to 2/2/4 chip selects) ? 1 flexcan interface (2 .0b active) with 32 message buffers ? one 10-bit analog-to-digital converter (adc) ? 7 input channels ? 4 channels routed to the pins ? 3 internal connections: 1x temperature sensor, 1x core voltage, 1x io voltage ? conversion time < 1 s including sampling time at full precision ? 4 analog watchdogs with interrupt capability ? on-chip can/uart bootstrap loader with boot assist module (bam) ? on-chip tsens ? 100 mbps automotive ethernet transceiver ? supports precision timestamps ? jpeg/mjpeg 8/12bit encoder ? 6 x stereo channels audio interface ? 2x i 2 c controller module ? crc module ? bcm89810 ethernet phy ? MPC5606E microcontroller data sheet
MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 2 table of contents 1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . .6 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.1 power supply and reference voltage pins . . . . . .7 2.2.2 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.3 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .18 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .19 3.4 recommended operating conditions . . . . . . . . . . . . . .20 3.5 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .21 3.5.1 general notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . . .22 3.6 electromagnetic interference (emi) characteristics . . .23 3.7 electrostatic discharge (esd) characteristics . . . . . . .23 3.8 power management electrical characteristics. . . . . . . .24 3.8.1 power management overview. . . . . . . . . . . . . .24 3.8.2 voltage regulator electrical characteristics . . . .26 3.8.3 voltage monitor electrical characteristics. . . . . .28 3.9 power up/down reset sequencing . . . . . . . . . . . . . . . .28 3.10 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . .30 3.11 main oscillator electrical characteristics . . . . . . . . . . . .31 3.12fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 3 2 3.13 16 mhz rc oscillator electric al characteristics . . . . . . 34 3.14 analog-to-digital converter (a dc) electrical characteristics 35 3.14.1 input impedance and adc accuracy . . . . . . . . 35 3.14.2 adc conversion characteristics . . . . . . . . . . . . 40 3.15 temperature sensor electrical characteristics . . . . . . . 41 3.16 flash memory electrical charac teristics . . . . . . . . . . . 41 3.17 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.17.1 pad ac specifications. . . . . . . . . . . . . . . . . . . . 44 3.18 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . 47 3.18.1 generic timing diagrams . . . . . . . . . . . . . . . . . 47 3.18.2 reset_b pin characteristics . . . . . . . . . . . . . . 48 3.18.3 nexus and jtag timing . . . . . . . . . . . . . . . . . . 49 3.18.4 gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.18.5 external interrupt timing (irq pin) . . . . . . . . . . 52 3.18.6 flexcan timing . . . . . . . . . . . . . . . . . . . . . . . . 52 3.18.7 linflex timing . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.18.8 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.18.9 video interface timing. . . . . . . . . . . . . . . . . . . . 58 3.18.10fast ethernet interface. . . . . . . . . . . . . . . . . . . 59 3.18.11i 2 c timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.18.12sai timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.1 121 mapbga mechanical outline drawing . . . . . . . . . 65
overview MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 3 1 overview this document provides electri cal specifications, pin assignmen ts, and package diagrams fo r the MPC5606E series of microcontroller units (mcus). MPC5606E microcontrollers are members of a new family of ne xt generation microcontrollers built on the power architecture. this document describes the features of the family and options available within the family members, and highlights important electrical and physical char acteristics of the devices. the MPC5606E microcontroller integrates mpc5604e device with the broadcom (r) bcm89810 single-port broadr-reach? 100 mbps automotive ethernet transceive r. all information about configuration of the bcm 89810 broadr-reach? ethernet transceivers is available at https://support.broadcom.com/ . the user should request fo r an account to access bcm89810 documentation, if the access is not there. the MPC5606E microcontroller is a gateway system designed to move data from diff erent sources via ethernet to a receiving system and vice versa. the supported data sources and sinks are: ? video data (with 8/10/12 bits per data word) ? audio data (6 ? stereo channels) ? radar data (2 ? 12 bit with <1 ? s per sample, digitized extern ally and read in via spi) ? other serial communica tion interfaces including can, lin, and spi the ethernet module has a bandwidth of 10/100 mbits/sec and support s precision time stamps (ieee 1588). unshielded twisted pair cables are used to transfer data (via ethernet) in the car, resulting in a significant reduction of wiring costs by provid ing inexpensive high bandwidth data links. 1.1 device summary table 1 summarizes the MPC5606E device. table 1. device summary feature MPC5606E 121 mapbga cpu e200z0h, 64 mhz, vle only, no spe flash with ecc cflash: 512 kb (lc) dflash: 64 kb (lc, area optimized) ram with ecc 96 kb dma 16 channels pit yes swt yes fcu yes ethernet 100 mbits mii-lite video encoder 8bpp/12bpp audio interface 6x stereo (4x synchrono us + 2x synchronous/asynchronous) adc (10-bit) 1 ?? 4 channels + v dd_io + v ddcore + tsens + vgate current 1 timer i/o (etimer) 1 ? 6 channels sci (linflex) 2 ?
MPC5606E microcontroller data sheet, rev. 3 overview freescale semiconductor 4 1.2 block diagram figure 1 shows a top-level block diagram of the MPC5606E mcu. spi (dspi) dspi_0: 2 chip selects dspi_1: 2 chip selects dspi_2: 4 chip selects can (flexcan) 1 ? iic 2 ? supply 3.3 v io 1.2v core with dedicated balla st source pin in two modes: ? internal ballast or ? external supply (using power on reset pin) phase lock loop (pll) 1 ? fmpll internal rc oscillator 16 mhz external crystal oscillator 4 mhz - 40 mhz crc yes debug jtag ambient temperature ?40 to 125 c 1 this feature is supported by design, but subject to confirmation after device characterization. table 1. device summary (continued) feature MPC5606E 121 mapbga
overview MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 5 figure 1. MPC5606E block diagram e200z0 core 32-bit general purpose registers special purpose registers integer execution unit exception handler variable length encoded instructions instruction unit load/store unit branch prediction unit 1.2 v regulator control xosc 16 mhz rc oscillator jtag port interrupt controller edma 16 channels master master instruction bus master data bus 512 kb slave slave crossbar switch (xbar, amba 2.0 v6 ahb) peripheral bridge etimer adc adc analog-to-digital converter bam boot assist module crc cylic redundancy check dspi deserial serial peripheral interface edma enhanced direct memory access etimer enhanced timer fcd fractional clock divider fcu fault collection unit fec fast ethernet controller flexcan flexible controller area network fmpll frequency-modulated phase-locked loop i2c inter-integrated circuit serial interface sai serial audio interface 6xstereo linflex serial communication interface (lin support) cgm clock generation module pcu power control unit rgm reset generation module tsens temperature sensor mjpeg 12-bit motion jpeg encoder pdi parallel data interface (image sensor) pit periodic interrupt timer ptp ieee 1588 precision time stamps siu system integration unit sram static random-access memory sscm system status and configuration module stm system timer module swt software watchdog timer 10-bit slave jtag (32-bit) (32-bit) 4+4 channels 2 x linflex flexcan crc 3 x i 2 c 3 x sai fcd sscm pit stm swt code flash (ecc) 64 kb data flash (ecc) 96 kb sram (ecc) output mjpeg pdi slave fmpll (system) internal and external ballast video_clk 3 x dspi buffer bam siu fcu cgm rgm pcu tsens me me mode entry module fec master ptp mii br-100 broadcom (r) 89810bcm ehernet phy
MPC5606E microcontroller data sheet, rev. 3 package pinouts and signal descriptions freescale semiconductor 6 2 package pinouts and signal descriptions 2.1 package pinouts the 121 mapbga pinouts are shown in the following figure. figure 2. 121 mapbga pinout(top view)
package pinouts and signal descriptions MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 7 2.2 signal descriptions the following sections provide signal descriptions and relate d information about the functionality and configuration of the MPC5606E devices. 2.2.1 power supply and reference voltage pins table 2 lists the power supply and reference voltage for the MPC5606E devices. table 2. supply pins supply pin port pin multi-bonded power supplies/ground description 121 mapbga vreg control and power supply pins. pins available on 121 mapbga-pin package. v dd_hv_s_bal last v dd_hv_s_ballast0 ballast source/supply voltage k5 adc0 reference and supply voltage. pins available on 121 mapbga-pin package. v dd_hv_adc v dd_hv_adr0 adc0 high reference voltage with respect to ground (v ss_hv_adc ) k4 power supply pins (3.3 v). pins av ailable on 121 m apbga-pin package. v dd_hv v dd_hv_fla1 code and data flash supply voltage j11 v dd_hv v dd_hv_fla0 code and data flash supply voltage a6 v dd_hv v dd_hv_osc0_reg0 code and data flash supply voltage g1 power supply pins (1.2 v). pins av ailable on 121 m apbga-pin package. v dd_lv v dd_lv_pll0 1.2 v pll supply voltage f1 v dd_lv v dd_lv_cor0_1 1.2 v supply pins for core logic and code flash. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor0_1 pin. k11 v ss_lv v ss_lv_cor0_2 1.2 v supply pins for core logic and code flash. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor0_2 pin. a5 bcm89810 supply pins. ovdd_rgmii pwr 2.5v or 3.3 v for rgmii pads; 3.3v for mii pads. f7 ovdd pwr 2.5 v or 3.3v for non rg mii pads. when 2.5v is selected, reset, mdio, and led pins are not 3.3v tolerant c5 dvdd pwr 1.2v power for digital core. d5, e6 avddl pwr 1.2v power for analog core. k6 avdd pwr 3.3v power for analog core. j5
MPC5606E microcontroller data sheet, rev. 3 package pinouts and signal descriptions freescale semiconductor 8 2.2.2 system pins table 3 and table 4 contain information on pin functions for the MPC5606E devices. the pins listed in table 3 are single-function pins. the pins shown in table 4 are multi-function pins, programmable via their respective pad configuration register (pcr) values. xtalvdd pwr 3.3v crystal supply. g4 pllvdd pwr 1.2v pll supply. k3 biasvdd pwr bias vdd. +3.3v. normally fi ltered with a low resistance ferrite bead such as a murata? blm11a601s or equivalent, as well as a 0.1f capacitor. h4 table 2. supply pins (continued) supply pin port pin multi-bonded power supplies/ground description 121 mapbga
package pinouts and signal descriptions MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 9 2.2.3 pin muxing table 4 defines the pin list and muxing for the MPC5606E devices. each row of table 4 shows all the possible ways of configuring each pin, via ?alternate functio ns?. the default function assigned to each pin after reset is the alt0 function.pins marked as external interrupt capable can also be used to resume from stop and halt mode. MPC5606E devices provide four main i/o pad types depending of the associated functions: table 3. system pins symbol description direction 121ma pbga mp5604e dedicated pins nmi non-maskable interrupt input only d2 xtal oscillator amplifier output output only g3 extal input for oscillator amplifier circuit and internal clock generator input only h2 tdi 1 1 additional board pull resistors are recommended when jtag pins are not being used on the board or application. jtag test data input input only j9 tms 1 jtag state machine control input only h11 tck 1 jtag clock input only j8 tdo 1 jtag test data output output only f9 reset pin reset_b bidirectional reset with schmitt trigger characteristics and noise filter bidirectional h3 por_b power-on reset input only l10 bcm89810 supply pins reset_n reset. active-low, schmitt trigger input. the bcm89810 requires a hardware reset prior to normal operation. configuration settings obtained via hardware strap option pins are latched on the rising edge of reset. i/o pu , cs, st c2 xtali 25 mhz crystal oscillator input/output. a continuous 25 mhz reference clock must be supplied to the bcm89810 by connecting a 25 mhz crystal between these two pins or by driving xtali with an external 25 mhz clock. when using a crystal, connect a loading capacitor from each pin to gnd. i/xt h7
MPC5606E microcontroller data sheet, rev. 3 package pinouts and signal descriptions freescale semiconductor 10 ? slow pads are the most common, providing a compromise between transition tim e and low electromagnetic emission. ? medium pads provide fast enough transition for serial communication channels w ith controlled current to reduce electromagnetic emission. ? fast pads provide maximum speed. they are used for improved nexus debugging capability. medium and fast pads can be used in slow configuration to re duce the electromagnetic emissions, at the co st of reducing ac performance. table 4. pin muxing mpc5 604e port pin pcr register alternate function 1,2,6 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 121 mapbg a port a (16-bit) a[0] pcr[0] alt0 alt1 alt2 alt3 ? ? ? gpio[0] d[0] ? ? d[11] sin eirq[0] siul sai0 ? ? vid dspi 1 siul i/o i/o ? ? i i i slow medium d1 a[1] pcr[1] alt0 alt1 alt2 alt3 ? ? gpio[1] d[1] sout ? d[10] eirq[1] siul sai0 dspi1 ? vid siul i/o i/o o ? i i slow medium d4 a[2] pcr[2] alt0 alt1 alt2 alt3 ? ? ? gpio[2] d[2] sck d[0] d[9] etc[5] eirq[2] siul sai0 dspi1 sai1 vid etimer0 siul i/o i/o i/o i/o i i i slow medium e4 a[3] pcr[3] alt0 alt1 alt2 alt3 ? ? ? gpio[3] d[3] ? d[0] d[8] sin eirq[3] siul sai0 ? sai2 vid dspi2 siul i/o i/o ? i/o i i i slow medium e1 a[4] pcr[4] alt0 alt1 alt2 alt3 ? ? ? gpio[4] sync sout ? d[7] etc[3] eirq[4] siul sai0 dspi2 ? vid etimer0 siul i/o i/o o ? i i i slow medium e3
package pinouts and signal descriptions MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 11 a[5] pcr[5] alt0 alt1 alt2 alt3 ? ? ? gpio[5] sync sck d[0] clk etc[4] eirq[5] siul sai1 dspi2 sai1 vid etimer0 siul i/o i/o i/o i/o i i i medium fast e2 a[6] pcr[6] alt0 alt1 alt2 alt3 ? ? ? ? gpio[6] sync cs0 ? vsync d[0] etc[1] eirq[6] siul sai2 dspi2 ? vid vid etimer0 siul i/o i/o i/o ? i i i i slow medium f2 a[7] pcr[7] alt0 alt1 alt2 alt3 ? ? ? ? gpio[7] bclk cs1 ? href d[1] etc[2] eirq[7] siul sai0 dspi2 ? vid vid etimer0 siul i/o i/o i/o ? i i i i slow medium h1 a[8] pcr[8] alt0 alt1 alt2 alt3 ? ? ? gpio[8] bclk cs0 d[0] d[6] rx eirq[8] siul sai1 dspi1 sai2 vid lin1 siul i/o i/o i/o i/o i i i slow medium h5 a[9] pcr[9] alt0 alt1 alt2 alt3 ? ? gpio[9] bclk cs1 tx d[5] eirq[9] siul sai2 dspi1 lin1 vid siul i/o i/o i/o o i i slow medium j6 a[10] pcr[10] alt0 alt1 alt2 alt3 ? ? ? gpio[10] mclk etc[5] ? d[4] sin eirq[10] siul sai2 etimer0 ? vid dspi0 siul i/o i/o i/o ? i i i slow medium l9 table 4. pin muxing (continued) mpc5 604e port pin pcr register alternate function 1,2,6 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 121 mapbg a
MPC5606E microcontroller data sheet, rev. 3 package pinouts and signal descriptions freescale semiconductor 12 a[11] pcr[11] alt0 alt1 alt2 alt3 ? ? ? gpio[11] tx cs1 cs0 d[3] rx rx siul can0 dspi0 dspi1 vid lin0 lin1 i/o o o i/o i i i slow medium k7 a[12] pcr[12] alt0 alt1 alt2 alt3 ? ? ? gpio[12] tx cs0 tx d[2] rx eirq[11] siul lin0 dspi0 lin1 vid can0 siul i/o o i/o o i i i slow medium k9 a[13] pcr[13] alt0 alt1 alt2 alt3 ? gpio[13] clk f[0] cs0 eirq[12] siul iic1 fcu0 dspi0 siul i/o i/o o i/o i slow medium k8 a[14] pcr[14] alt0 alt1 alt2 alt3 ? ? gpio[14] data f[1] cs1 sin eirq[13] siul iic1 fcu0 dspi0 dspi0 siul i/o i/o o o i i slow medium k10 a[15] pcr[15] alt0 alt1 alt2 alt3 ? ? ? gpio[15] sck pps3 mclk sck etc[0] eirq[18] siul dspi0 ce_rtc sai1 dspi1 etimer0 siul i/o i/o o i/o i i i slow medium a3 port b (16-bit) b[0] pcr[16] alt0 alt1 alt2 alt3 ? gpio[16] tx alarm2 bclk an[0] siul can0 ce_rtc sai1 adc0 6 i/o o o i/o i slow medium l2 b[1] pcr[17] alt0 alt1 alt2 alt3 ? ? ? gpio[17] ? ? d[0] an[1] rx trigger2 siul ? ? sai1 adc0 6 can0 ce_rtc i/o ? ? i/o i i i slow medium k1 table 4. pin muxing (continued) mpc5 604e port pin pcr register alternate function 1,2,6 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 121 mapbg a
package pinouts and signal descriptions MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 13 b[2] pcr[18] alt0 alt1 alt2 alt3 ? ? gpio[18] tx pps2 alarm1 an[2] trigger1 siul lin0 ce_rtc ce_rtc adc0 6 ce_rtc i/o o o o i i slow medium k2 b[3] pcr[19] alt0 alt1 alt2 alt3 ? ? ? gpio[19] etc[2] sout pps1 an[3] rx eirq[14] siul etimer0 dspi0 ce_rtc adc0 6 lin0 siul i/o i/o i/o o i i i slow medium j2 b[4] pcr[20] alt0 alt1 alt2 alt3 ? gpi[20] ? ? ? rx_dv siul ? ? ? fec i ? ? ? i slow medium g8 b[5] pcr[21] alt0 alt1 alt2 alt3 gpio[21] tx_d0 debug[0] ? siul fec sscm ? i/o o i/o ? slow medium g10 b[6] pcr[22] alt0 alt1 alt2 alt3 gpio[22] tx_d1 debug[1] ? siul fec sscm ? i/o o i/o ? slow medium g11 b[7] pcr[23] alt0 alt1 alt2 alt3 gpio[23] tx_d2 debug[2] ? siul fec sscm ? i/o o i/o ? slow medium e9 b[8] pcr[24] alt0 alt1 alt2 alt3 gpio[24] tx_d3 debug[3] ? siul fec sscm ? i/o o i/o ? slow medium f11 b[9] pcr[25] alt0 alt1 alt2 alt3 gpio[25] tx_en debug[4] ? siul fec sscm ? i/o o i/o ? slow medium e11 b[10] pcr[26] alt0 alt1 alt2 alt3 gpio[26] mdc debug[5] ? siul fec sscm ? i/o o i/o ? slow medium d11 table 4. pin muxing (continued) mpc5 604e port pin pcr register alternate function 1,2,6 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 121 mapbg a
MPC5606E microcontroller data sheet, rev. 3 package pinouts and signal descriptions freescale semiconductor 14 b[11] pcr[27] alt0 alt1 alt2 alt3 gpio[27] mdio debug[6] ? siul fec sscm ? i/o i/o i/o ? slow medium c10 b[12] pcr[28] alt0 alt1 alt2 alt3 ? gpio[28] ? debug[7] ? tx_clk siul ? sscm ? fec i/o ? i/o ? i slow medium a10 b[13] pcr[29] alt0 alt1 alt2 alt3 ? gpi[29] ? ? ? rx_d0 siul ? ? ? fec i ? ? ? i slow medium b8 b[14] pcr[30] alt0 alt1 alt2 alt3 ? gpi[30] ? ? ? rx_d1 siul ? ? ? fec i ? ? ? i slow medium c7 b[15] pcr[31] alt0 alt1 alt2 alt3 ? gpi[31] ? ? ? rx_d2 siul ? ? ? fec i ? ? ? i slow medium d8 port c (7 bit) c[0] pcr[32] alt0 alt1 alt2 alt3 ? gpi[32] ? ? ? rx_d3 siul ? ? ? fec i ? ? ? i slow medium c6 c[1] pcr[33] alt0 alt1 alt2 alt3 ? ? gpi[33] ? ? ? rx_clk eirq[15] siul ? ? ? fec siul i ? ? ? i i slow medium a7 c[2] pcr[34] alt0 alt1 alt2 alt3 ? ? ? gpio[34] etc[0] tx pps1 d[0] rx eirq[16] siul etimer0 can0 ce_rtc vid lin0 siul i/o i/o o o i i i slow medium b6 table 4. pin muxing (continued) mpc5 604e port pin pcr register alternate function 1,2,6 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 121 mapbg a
package pinouts and signal descriptions MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 15 the following conventions are used in the following table: ? i = input ? o = output ? i/o = bidirectional ? ot = tristateable signal c[3] pcr[35] alt0 alt1 alt2 alt3 ? ? ? gpio[35] etc[1] tx sync d[1] rx eirq[17] siul etimer0 lin0 sai1 vid can0 siul i/o i/o o i/o i i i slow medium a2 c[4] pcr[36] alt0 alt1 alt2 alt3 ? ? ? gpio[36] clk_out etc[4] mclk trigger1 abs[0] eirq[19] siul mc_cgl etimer0 sai0 ce_rtc mc_rgm siul i/o o i/o i/o i i i medium fast g6 c[5] pcr[37] alt0 alt1 alt2 alt3 ? ? gpio[37] clk etc[3] cs2 abs[2] eirq[20] siul iic0 etimer0 dspi2 mc_rgm siul i/o ? i/o o i i slow medium b2 c[6] pcr[38] alt0 alt1 alt2 alt3 ? ? gpio[38] data cs0 cs3 fab eirq[21] siul iic0 dspi1 dspi2 mc_rgm siul i/o ? i/o o i i slow medium b1 1 alt0 is the primary (default) function for each port after reset. 2 alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siu module. pcr.pa = 00 ? alt0; pcr.pa = 01 ? alt1; pcr.pa = 10 ? alt2; pcr.pa = 11 ? alt3. this is intended to select the output functions; to use one of the input func tions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfie lds. for this reason, the value corresponding to an input only function is reported as ???. 3 module included on the mcu. 4 multiple inputs are routed to all respec tive modules internally. the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 5 programmable via the src (slew rate control) bits in the respective pad configuration register. 6 do not use alt multiplexing when adc channels are used. table 4. pin muxing (continued) mpc5 604e port pin pcr register alternate function 1,2,6 functions peripheral 3 i/o direction 4 pad speed 5 pin src = 0 src = 1 121 mapbg a
MPC5606E microcontroller data sheet, rev. 3 package pinouts and signal descriptions freescale semiconductor 16 ?b = bias ? pu = internal pull-up ? pd = internal pull-down ? sor = sample on reset ? cs = continuously sampled ? st = schmitt trigger ? xt = crystal inputs/outputs pin type ? a = analog pint type ? d = digital pin type ? g = rgmii pin type table 5. pin muxing for bcm89810 functions i/o type 121 mapbga gtx_clk i pd ot g a9 led1 i pu, oc3 led2 i pu, ob3 led3 i pu, ob4 led4 i pu, oc4 mdc i pd , st c11 mdio i/o pu , d, st b10 phya0 i pd , sor b5 rdac b l7 reset_n i pu , cs, st c2 rxc ot, g b7 rxd0 ot, g b9 rxd1 ot, g c9 rxd2 ot, g d9 rxd3 ot, g d7 rxdv ot, g h8 tdn0 a, a l4 tdp0 a, a l5 test2 i pd , cs f5 test3 i pd , cs f3 tvcoi o j3
package pinouts and signal descriptions MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 17 txd0 i pd , gh9 txd1 i pd , gh10 txd2 i pd , ge8 txd3 i pd , gf10 txen i pd , ge10 xtali i/xt h7 table 5. pin muxing (continued)for bcm89810 functions i/o type 121 mapbga
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 18 3 electrical characteristics 3.1 introduction this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this can be done by the internal pull-up or pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. 3.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 3 are used and the parameters are ta gged accordingly in the tables where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 3. paramete r classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 19 3.3 absolute maximum ratings table 4. absolute maximum ratings 1 symbol parameter conditions min max 2 unit v ss sr device ground ? v ss v ss v v dd_hv_io sr 3.3 v input/output supply voltage (supply). code flash supply with v dd_hv_io3 and data flash with v dd_hv_io2 ?v ss _ 0.3 v ss + 6.0 v v ss_hv_io sr 3.3 vinput/output supply voltage (ground). code flash ground with v ss_hv_io3 and data flash with v ss_hv_io2 ?v ss _ 0.1 v ss + 0.1 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage (supply) the oscillator and flash supply segments are double-bounded with the v dd_hv_io segments. see v dd_hv_io and v ss_hv_io specifications. ? v ss_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage (ground) v dd_hv_adc0 3 sr 3.3 v adc_0 supply and high reference voltage ?v ss _ 0.3 v ss + 6.0 v v ss_hv_adc0 sr 3.3 v adc_0 ground and low reference voltage ?v ss _ 0.1 v ss + 0.1 v v dd_hv_reg sr 3.3 v voltage regulator supply voltage ?v ss _ 0.3 v ss + 6.0 v tv dd sr slope characteristics on all vdd during power up 4 ?? 0.1v/us v dd_lv_cor sr 1.2 v supply pins for core logic (supply) ?v ss _ 0.3 v ss + 1.4 v v ss_lv_cor sr 1.2 v supply pins for core logic (ground) ?v ss _ 0.1 v ss + 0.1 v v in sr voltage on any pin with respect to ground (v ss_hv_io ) ?v ss_hv_io _ 0.3 v dd_hv_io +0.5 v i injpad sr input current on any pin during overload condition ??10 10ma i injsum sr absolute sum of all input currents during overload condition ??50 50ma t storage sr storage temperature ? ?55 150 c t j sr junction temperature under bias ? ?40 132 c t a sr ambient temperature under bias f cpu <64 mhz ?40 125 c f cpu <64 mhz video use case with internal supply ?40 105 c bcm89810 absolute maximum ratings ovdd supply voltage gnd-0.3 3.8 v
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 20 3.4 recommended operating conditions note for bcm89810 document please refer to broadcom website and download the document avdd supply voltage gnd-0.3 3.8 v biasvdd supply voltage gnd-0.3 3.8 v xtalvdd supply voltage gnd-0.3 3.8 v avddl supply voltage gnd-0.3 1.4 v dvdd supply voltage gnd-0.3 1.4 v t stg storage temperature -40 125 c v esd esd protection -2500 2500 v 1 functional operating conditions are given in the dc electric al characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 absolute maximum voltages are currently maximum burn-in voltages. absolute maximum specifications for device stress have not yet been determined. 3 MPC5606E?s i/o, flash, and oscillator circuit supplie s are interconnected. the adc supply managed independently from other supplies. 4 guaranteed by device validation. table 5. recommended operating conditions symbol parameter conditions min max 1 unit v ss sr device ground ? v ss v ss v v dd_hv_io sr 3.3 v input/output supply voltage ? 3.0 3.6 v v ss_hv_io sr input/output ground voltage ? 0 0 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage (supply) the oscillator and flash supply segments are double-bounded with the v dd_hv_iox segments. see v dd_hv_iox and v ss_hv_iox specifications. ? v ss_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage (ground) v dd_hv_adc0 2 sr 3.3 v adc_0 supply and high reference voltage ?3.03.6v v dd_hv_reg sr 3.3 v voltage regulator supply voltage ? 3.0 3.6 v v dd_lv_extcor sr externally supplied core voltage ? 1.15 1.32 v v dd_lv_regcor sr internal supply voltage ? ? ? v v ss_lv_regcor sr internal reference voltage ? 0 0 v v dd_lv_cor sr internal supply voltage ? ? ? v v ss_lv_cor sr internal reference voltage ? 0 0 v table 4. absolute maximum ratings 1 (continued) symbol parameter conditions min max 2 unit
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 21 3.5 thermal characteristics 3.5.1 general notes for specification s at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : t j = t a + (r ? ja * p d ) eqn. 1 where: v ss_hv_adc0 sr ground and low reference voltage ? 0 0 v t j sr junction temperature under bias ?40 132 c t a sr ambient temperature under bias f cpu <64 mhz ?40 125 c f cpu <64 mhz video use case with internal supply ?40 105 c 1 full functionality cannot be guaranteed wh en voltage drops below 3.0 v. in particular, adc electrical characteristics and i/os dc electrical specification may not be guaranteed. 2 MPC5606E?s i/o, flash, and oscillator circuit supplies are interconnected. the adc supply managed independently from other supplies. table 6. thermal characteristics for 121 mapbga symbol parameter conditions typical value unit r ? ja junction to ambient natural convection 12 1 junction-to-ambient thermal resistance determi ned per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 2 junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. single layer board?1s 42.46 c/w r ? ja junction to ambient natural convection 123 3 junction-to-case at the top of the package determin ed using mil-std 883 meth od 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. four layer board?2s2p 27.18 c/w r ? jma junction to ambient (@200 ft/min) 13 single layer board?1s 34.67 c/w four layer board?2s2p 23.75 c/w r ? jb junction to board 2 ? 21.27 c/w r ? jctop junction to case 3 ? 11.88 c/w ? jt junction to package top 4 4 thermal characterization parameter indicating the tem perature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt natural convection 0.12 c/w table 5. recommended operating conditions (continued) symbol parameter conditions min max 1 unit
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 22 t a = ambient temperature for the package (c) r ? ja = junction to ambient th ermal resistance (c/w) p d = power dissipation in the package (w) the junction to ambient th ermal resistance is an industry st andard value that provides a quick and easy estimation of thermal performance. there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be diff erent by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usuall y appropriate if the board has low power dissi pation and the components are well separated. when a heat sink is used, the th ermal resistance is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ? ja = r ? jc + r ? ca eqn. 2 where: r ? ja = junction to ambient thermal resistance (c/w) r ? jc = junction to case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) r ? jc is device related and cannot be influenced by the user. the user controls the thermal envi ronment to change the case to ambient thermal resistance, r ? ca . for instance, the user can change the size of th e heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in th e application when heat sink s are not used, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using equation 3 : t j = t t + ( ? jt x p d ) eqn. 3 where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple juncti on and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 u.s.a. (408) 943-6900 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. 1. c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module , proceedings of semitherm, san diego, 1998, pp. 47-54.
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 23 2. g. kromann, s. shidore, and s. addison, thermal modeling of a pbga for air-cooled applications , electronic packaging and production, pp. 53-58, march 1998. 3. b. joiner and v. adams, measurement and simulation of junction to board thermal resistance and its application in thermal modeling , proceedings of semitherm, san diego, 1999, pp. 212-220. 3.6 electromagnetic interference (emi) characteristics 3.7 electrostatic discharge (esd) characteristics table 7. emi testing specifications 1 1 emi testing and i/o port waveforms per standard iec61967-2. symbol parameter conditions clocks frequency range level (typ) unit radiated emissions v eme v dd = 3.3 v t a =+25c device configuration, test conditions and em testing per standard iec61967-2. oscillator frequency = 8 mhz; system bus frequency = 64 mhz; cpu freq = 64mhz no pll frequency modulation 150 khz?50 mhz 2 db ? v 50?150 mhz 14 150?500 mhz 11 500?1000 mhz 7 iec level m external oscillator freq = 8 mhz system bus freq = 64 mhz cpu freq = 64mhz 2% pll freq modulation 150 khz?50 mhz 1 db ? v 50?150 mhz 11 150?500 mhz 7 500?1000 mhz 1 iec level n table 8. esd ratings 1,2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and f unctional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification symbol parameter conditions value unit v esd(hbm) sr electrostatic discharge (human body model) ? 2000 v v esd(cdm) sr electrostatic discharge (charged device model) ? 750 (corners) v 500 (other)
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 24 3.8 power management electrical characteristics 3.8.1 power management overview the device supports the following power modes: ? internal voltage regulation mode ? external voltage regulation mode 3.8.1.1 mpc5604e internal voltage regulation mode in this mode, the following supplies are involved: ?v dd_hv_io (3.3v) ? this is the main supply provided externally. note 1.2v is not generated internally for bcm89810 so the user has to use external power supply mode for applications where bcm89810 is used. ?v dd_lv_cor (1.2v) ? this is the core logic supply. in the internal regulation mode, the core supply is derived from the main supply via an on-chip linear regulator driving an internal pmos ballast tr ansistor. the pmos ballast transistors are located in the pad ri ng and their source connect ors are directly bonded to a dedicated pin. see figure 6 . figure 6. internal regulation mode the core supply can also be provided externally. table 9 shows how to connect v dd_hv_s_ballast pin for internal and external core supply mode.
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 25 note v dd_hv_s_ballast pin is the supply pin, which carries the entire core logic current in the internal regulation mode, while in external regu lation mode it is used as a signal to bypass the regulator. 3.8.1.2 mpc5604e external voltage regulation mode in the external regulation mode, the core supply is provided ex ternally using a switched regulator. this saves on-chip power consumption by avoiding the voltage drop over the ballast transi stor. the external supply mode is selected via a board level supply change at the v dd_hv_s_ballast pin. figure 7. external regulation mode table 9. core supply select mode v dd_hv_s_ballast internal supply mode (via internal pmos ballast transistors) v dd_hv_io (3.3v) external supply mode (e.g., via external switched regulator) v dd_lv_cor (1.2v)
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 26 3.8.1.3 recommended power supply sequencing 1 for MPC5606E, the external supplies need to be maintained as per the following relations: ?v dd_hv_io should be always greater or equal to v dd_hv_s_ballast ?v dd_hv_io should be always greater than v dd_lv_cor0_x ?v dd_hv_io should be always greater than v dd_hv_adc 3.8.2 voltage regulator electrical characteristics \ figure 8. voltage regulator capacitance connection 1.investigations are in process to rela x power supply sequencing recommendation. table 10. voltage regulator electrical characteristics symbol c parameter conditions 1 value unit min typ max c regn 2 sr ? internal voltage regulator external capacitance ? 200 ? 600 nf r reg sr ? stability capacitor equivalent serial resistance ?0.05?0.2 ? c reg1 (lv_cor/lv_dfla) device v ss_hv_io c dec1 (ballast decoupling) v dd_hv_io v ss_lv_cor0_2 c reg2 (lv_cor/lv_cfla) c reg3 (lv_cor/lv_pll) c dec2 (supply/io decoupling) device i v ref v dd_hv_io voltage regulator v ss_hv_io gnd gnd gnd gnd v dd_hv_s_ballast1 v dd_lv_cor0_1 600 nf 600 nf v dd_hv_s_ballast0 v dd_lv_cor0_0 v ss_lv_cor0_0 v dd_lv_cor0_2 v ss_lv_cor0_1 - + v dd_lv_cor0_3
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 27 3.8.3 voltage monitor electrical characteristics the device implements a por module to en sure correct power-up initia lization, as well as thr ee low voltage detectors to monitor the v dd_hv and the v dd_lv voltage while device is supplied: ? por monitors v dd_hv during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd_hv to ensure device reset below minimum functional supply ? lvdlvcor monitors low voltage digital power domain c dec1 sr ? decoupling capacitance 3 ballast ? 100 4 470 5 ?nf ? 400 ? c dec2 sr ? decoupling capacitance regulator supply ? 100 nf 1 ? f?? v mreg cc t main regulator output voltage before exiting from reset ? 1.32 ? v p after trimming 1.15 1.28 1.32 i mreg sr ? main regulator current provided to v dd_lv domain ??? 150 ma i mregint cc d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 i dd_bv cc d in-rush current on v dd_bv during power-up 6 ?? ? 40 7 ma 1 v dd = 3.3 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 it is required by the device in internal voltage regulation mode only. 3 this capacitance value is driven by the constraints of the external voltage r egulator that supplies the v dd_bv voltage. a typical value is in the range of 470 nf. this capacitance should be placed close to the device pin. 4 this value is acceptable to guar antee operation from 3.0 v to 3.6 v 5 external regulator and capacitance circuitry must be capable of providing i dd_bv while maintaining supply v dd_bv in operating range. 6 in-rush current is seen only for short time during power-up and on standby exit (max 20 s, depending on external lv capacitances to be load) 7 the duration of the in-rush current depends on the capac itance placed on lv pins. bv decaps must be sized accordingly. refer to imreg value for minimum amount of current to be provided in cc. table 11. low voltage monitor electrical characteristics symbol parameter conditions 1 value unit min max v porh t power-on reset threshold ? 1.5 2.7 v v porup d supply for functional por module t a = 25c 1.0 ? v v ddhvlvdmok_h p v dd_hv low voltage detector high threshold ? ? 2.95 v v ddhvlvdmok_l pv dd_hv low voltage detector low threshold ? 2.6 ? v table 10. voltage regulator electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 28 3.9 power up/down reset sequencing the MPC5606E implements a precise sequen ce to ensure each module is started onl y when all conditions for switching it on are available. for bcm89810 clock on xtali clock input pad before reset_n is released. this prevents overstress event or miss-functionality within and outside the device: ? a por module working on voltage regulator supply is control ling the correct start-up of the regulator. this is a key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5 v. associated por (or por) signal is active low. ? several low voltage detectors, working on voltage regulator supply are monitoring the voltage of the critical modules (voltage regulator, i/os, flash and low voltage dom ain). lvds are gated low when power_on is active. ? a power_ok signal is generated when all critical supplies monitored by the lv d are available. th is signal is active high and released to all modules including i/os, flash a nd rc16 oscillator needed during power-up phase and reset phase. when power_ok is low the associat ed module are set into a safe state. figure 9. power-up typical sequence v mlvddok_h p digital supply low voltage detector high ? ? 1.235 v v mlvddok_l p digital supply low voltage detector low ? 1.095 ? v 1 v dd _ hv = 3.3v 10% t a = ?40 c to t a max , unless otherwise specified table 11. low voltage monitor electrical characteristics symbol parameter conditions 1 value unit min max vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 0v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 p1 0v 1.2v internal reset generation module fsm ~1us v por_up v porh v lvdhv3h v mlvdok_h
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 29 figure 10. power-down typical sequence vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l v porh 0v
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 30 3.10 dc electrical characteristics table 12 gives the dc electrical charact eristics at 3.3 v (3.0 v < v dd_hv_io < 3.6 v). note for bcm89810 document please refer to broadcom website and download the document table 12. dc electrical characteristics (3.3 v) 1 symbol parameter conditions min max unit v il d minimum low level input voltage ? ?0.4 2 ?v v il p maximum low level input voltage ? ? 0.35 v dd_hv_io v v ih p minimum high level input voltage ? 0.65 v dd_hv_io ?v v ih d maximum high level input voltage ??v dd_hv_io +0.4 2 v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_io ?v v ol_s p slow, low level output voltage i ol =2ma ? 0.1v dd_hv_io v v oh_s p slow, high level output voltage i oh =?2ma 0.8v dd_hv_io ?v v ol_m p medium, low level output voltage i ol =2ma ? 0.1v dd_hv_io v v oh_m p medium, high level output voltage i oh =?3ma 0.8v dd_hv_io ?v v ol_f p fast, high level output voltage i ol =11ma ? 0.1v dd_hv_io v v oh_f p fast, high level output voltage i oh = ?11 ma 0.8v dd_hv_io ?v i pu p equivalent pull-up current v in =v il ?95 ? a i pd p equivalent pull-down current v in =v ih ?95 i il p input leakage current (all bidirectional ports) t a = ?40 to 125 c ?1a i il p input leakage current (all adc input-only ports) t a = ?40 to 125 c ?0.5a v ilr d minimum reset , low level input voltage ? ?0.4 2 ?v v ilr p maximum reset , low level input voltage ? ?0.35v dd_hv_io v v ihr p minimum reset , high level input voltage ? 0.65 v dd_hv_io ?v v ihr d maximum reset , high level input voltage ? ?v dd_hv_io +0.4 2 v v hysr d reset , schmitt trigger hysteresis ? 0.1 v dd_hv_io ?v v olr d reset , low level output voltage i ol =0.5ma ? 0.1v dd_hv_io v i pu d reset , equivalent pull-up current v in =v il ?130 ? a v in =v ih ??10 c in d input capacitance ? ? 10 pf
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 31 3.11 main oscillator electrical characteristics the MPC5606E provides an oscillator/resonator driver. note for bcm89810 document please refer to broadcom website and download the document 1 these specifications are design targets and s ubject to change per device characterization. 2 ?sr? parameter values must not exceed the absolute maximum ratings shown in ta bl e 4 . table 13. supply current symbol parameter conditions value 1 1 all values to be confirmed after characterization/data collection. unit min typ max i dd_lv_core c supply current run mode, i/o currents not included, worst case over temperature for system clock ?75120ma p halt mode 2 2 halt mode configurations: code fetched fr om sram, code flash and data flash in low power mode, osc/pll0 are off, core clock frozen, all peripherals are disabled. v dd_lv_corx externally forced at 1.3 v ?425 pstop mode 3 3 stop "p" mode dut configuration: code fetched from sram, code flash and data flash off, osc/pll0 are off, core clock frozen, all peripherals are disabled. v dd_lv_corx externally forced at 1.3 v ?425 i dd_flash c code flash flash supply current during read v dd_hv_io at 3.3 v ? 4 7 flash supply current during erase operation on 1 flash module v dd_hv_io at 3.3 v ? 9 14 data flash flash supply current during read v dd_hv_io at 3.3 v ? 3.5 6 flash supply current during erase operation on 1 flash module v dd_hv_io at 3.3 v ? 7.5 12 i dd_adc c adc supply current v dd_hv_adc0 at 3.3 v adc freq = 16mhz ?1.83 i dd_osc c osc supply current v dd_hv_osc at 3.3 v 16 mhz ?0.74 4
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 32 3.12 fmpll electrical characteristics table 14. main oscillator electrical characteristics symbol parameter min max unit f osc sr oscillator frequency 4 40 mhz g m p transconductance 4 15.846 ma/v v osc t oscillation amplitude on xtal pin 1.3 2.25 v t oscsu t start-up time 1,2 1 the start-up time is dependent upon crystal characteristics, board leakage, etc., high esr and excessive capacitive loads can cause long start-up time. 2 value captured when amplitude reaches 90% of xtal ?5ms table 15. input clock characteristics symbol parameter min typ max unit f osc sr oscillator frequency 4 ? 40 mhz f clk sr frequency in bypass ? ? 100 mhz t rclk sr rise/fall time in bypass ? ? 1 ns t dc sr duty cycle 47.5 50 52.5 % table 16. pllmrfm electrical specifications 1 (v ddpll = 3.0 v to 3.6 v, v ss = v sspll = 0 v, t a = t l to t h ) symbol parameter conditions value unit min max f ref_crystal f ref_ext d pll reference frequency range 2 crystal reference 4 40 mhz f pll_in d phase detector input frequency range (after pre-divider) ?416mhz f fmpllo ut d clock frequency range in normal mode ? 4 120 mhz f vco p vco free running frequency measured using clock division?typicall y /16 20 150 mhz f sys d on-chip pll frequency 2 ?1664mhz t cyc d system clock period ? ? 1 / f sys ns f scm d self-clocked mode frequency 3,4 ? 20 150 mhz
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 33 c jitter tclkout period jitter 5,6,7,8 peak-to-peak (clock edge to clock edge) f sys maximum 500 500 ps long-term jitter (avg. over 2 ms interval) ?6 6 ns t lpll d pll lock time 9, 10 ? ? 200 ? s t dc d duty cycle of reference ?4060% f lck d frequency lock range ? ?6 6 % f sys f ul d frequency un-lock range ? ?18 18 % f sys f cs f ds d modulation depth center spread 0.25 4.0 11 %f sys down spread ?0.5 ?8.0 f mod d modulation frequency 12 ? ? 100 khz 1 all values given are initial design targets and subject to change. 2 considering operation with pll not bypassed. 3 self clocked mode frequency is the frequency that the pl l operates at when the refere nce frequency falls outside the f lor window. 4 f vco self clock range is 20-150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 5 this value is determined by the cr ystal manufacturer and board design. 6 jitter is the average deviation from the programmed frequ ency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 7 proper pc board layout procedures must be followed to achieve specifications. 8 values are with frequency modulation disabled. if frequ ency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 9 this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this pll, load capacitors s hould not exceed these limits. 10 this specification applies to the period required for the pl l to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 11 this value is true when operating at frequencies above 60 mhz, otherwise f cs is 2% (above 64 mhz). 12 modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 khz. table 16. pllmrfm electrical specifications 1 (v ddpll = 3.0 v to 3.6 v, v ss = v sspll = 0 v, t a = t l to t h ) (continued) symbol parameter conditions value unit min max
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 34 3.13 16 mhz rc oscillator electrical characteristics table 17. 16 mhz rc oscillator electrical characteristics symbol parameter conditions min typ max unit f rc c rc oscillator frequency t a = 25 c 8.5 16 24 mhz ? rcmvar p fast internal rc oscillator variation in temperature and supply with respect to f rc at t a = 55 c in high-frequency configuration ??5?5% ? rcmtrim t post trim accuracy: the variation of the ptf 1 from the 16 mhz oscillator 1 ptf = post trimming frequency: the frequency of the out put clock after trimming at typical supply voltage and temperature t a = 25 c ?2 ? 2 %
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 35 3.14 analog-to-digital converter (adc) electrical characteristics the device provides a 10-bit successive approximatio n register (sar) analog-to-digital converter. figure 11. adc characteristics and error definitions 3.14.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenua ting the noise present on the inpu t pin; further, it sources c harge during the sampling phase, when the analog si gnal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dd_adc / 1024
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 36 be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (fc ? c s ), where fc represents the conversion rate at the consid ered channel). to minimize th e error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 equation 4 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 12. input equivalent circuit a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 12 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? r f c f r s r l r sw1 c p2 v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 37 figure 13. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 5 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 ? a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 8 v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ?
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 38 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. figure 14. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 39 eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 12 v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 40 3.14.2 adc conversion characteristics table 18. adc conversion characteristics symbol parameter conditions 1 value unit min typ max f ck sr adc clock frequency (depends on adc configuration) (the duty cycle depends on adcclk 2 frequency) ?1?64mhz f s sr sampling frequency ? ? ? 1.53 mhz t adc_s d sample time 3 f adc = 20 mhz, adc_conf_sample_input = 17 500 ? ? ns f adc = 9 mhz, inpsamp = 255 ? ? 28.2 s t adc_c p conversion time 4 f adc = 20 mhz 5 , adc_conf_comp = 3 500 ? ? ns c s 6 d adc input sampling capacitance ???2.5pf c p1 6 d adc input pin capacitance 1 ? ? ? 0.8 7 pf c p2 6 d adc input pin capacitance 2 ? ? ? 1 pf r sw1 6 d internal resistance of analog source ???0.6k ? r ad 6 d internal resistance of analog source ???2k ? i inj t input current injection current injection on one adc input, different from the converted one. remains within tue specification ?5 ? 5 ma inl p integral non linearity no overload ?1.5 ? 1.5 lsb dnl p differential non linearity no overload ?1.0 ? 1.0 lsb ofs t offset error ? ? 1 ? lsb gne t gain error ? ? 1 ? lsb tue p total unadjusted error without current injection ??3?3lsb tue t total unadjusted error with current injection ??3?3lsb tue p total unadjusted error ? ?3 ? 3 lsb tuep cc total unadjusted error for precise channels, input only pins no overload -2 ? 2 lsb overload conditions on adjacent channel ??? lsb tuex cc total unadjusted error for extended channel, no overload -3 ? 3 lsb overload conditions on adjacent channel ??? lsb
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 41 3.15 temperature sensor electrical characteristics 3.16 flash memory electrical characteristics 1 v dd = 3.3 v to 3.6 v, t a = ?40 to +125 c, unless otherwise specified and analog input voltage from v agnd to v aref . 2 adcclk clock is always half of the adc module input clock defined via the auxiliary clock divider for the adc. 3 during the sample time the input capac itance cs can be charged/discharged by the external source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 4 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result register with the conversion result. 5 20 mhz adc clock. specific prescaler is programmed on mc_pll_clk to provide 20 mhz clock to the adc. 6 see figure 12 . 7 does not include packaging and bonding capacitances table 19. temperature sensor electrical characteristics symbol c parameter conditions value unit min typical max ? cc c temperature monitoring range ? ?40 ? 132 c ? cc c sensitivity ? ? 5.14 ? mv/c ? cc c accuracy t j = ?40 to 25 c ?10 ? 10 c ?ccc t j = ?25 to 125 c ?10 ? 10 c table 20. code flash program and erase specifications 1 symbol parameter min value typical value 2 (0 cycles) initial max 3 (100 cycles) max 4 (100000 cycles) unit t dwprg double word program 5 ? 22 50 500 ? s t bkprg bank program (512 kb) 5, 6 ? 1.45 1.65 33 s t er8k sector erase (8kb) ? 0.2 0.4 5.0 s t er16k sector erase (16kb) ? 0.3 0.5 5.0 s t er32k sector erase (32kb) ? 0.3 0.6 5.0 s t er64k sector erase (64kb) ? 0.6 0.9 5.0 s t er128k sector erase (128kb) ? 0.8 1.3 7.5 s t er512k bank erase (512kb) ? 4.8 7.6 55 s t pabt program abort latency ? ? 10 10 ? s t eabt erase abort latency ? ? 30 30 ? s
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 42 t eabt erase suspend latency ? ? 30 30 ? s t eabt erase suspend request rate 10 ? ? ? ms ner endurance (8kb, 16kb sectors) endurance (32kb, 64kb sectors) endurance (128kb sectors) 100 10 1 ? ? ? kcycles t dr data retention at 1k cycles data retenti on at 10k cycles data retenti on at 100k cycles 20 10 5 ? ? ? years 1 tbc = to be confirmed 2 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. 3 initial factory condition: < 100 program/er ase cycles, 25 c, typical supply voltage. 4 the maximum program & erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. 5 actual hardware programming times. this does not include software overhead. 6 typical bank programming time assumes that all cells are pr ogrammed in a single pulse. in reality some cells will require more than one pulse, adding a small overhead to total bank programming time (see initial max column). table 21. data flash program and erase specifications 1 1 tbc = to be confirmed symbol parameter min value typical value 2 (0 cycles) 2 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 3 (100 cycles) max 4 (100000 cycles) unit t dwprg word program 5 ?30tbctbc ? s t bkprg bank program (64 kb) 5, 6 ?0.49tbctbcs t er16k sector erase (16kb) ? 0.7 tbc tbc s t er512k bank erase (64kb) ? 1.9 tbc tbc s t pabt program abort latency ? ? 12 12 ? s t eabt erase abort latency ? ? 30 30 ? s t eabt erase suspend latency ? ? 30 30 ? s t eabt erase suspend request rate 10 ? ? ? ms ner endurance (16kb sectors) 100 ? ? ? k cycles t dr data retention at 1k cycles data retenti on at 10k cycles data retenti on at 100k cycles 20 10 1 ? ? ? years @85c table 20. code flash program and erase specifications 1 symbol parameter min value typical value 2 (0 cycles) initial max 3 (100 cycles) max 4 (100000 cycles) unit
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 43 3 initial factory condition: < 100 program/er ase cycles, 25 c, typical supply voltage. 4 the maximum program & erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. 5 actual hardware programming times. this does not include software overhead. 6 typical bank programming time assumes that all cells are pr ogrammed in a single pulse. in reality some cells will require more than one pulse, adding a small overhead to total bank programming time (see initial max column). table 22. flash read access timing symbol c parameter conditions 1 1 vdd_hv = 3.3 v 10%, ta = ?40 to 125 c, unless otherwise specified max unit fmax c maximum working frequency for code flash at given number of ws in worst conditions 2 wait states 66 mhz 0 wait states 18 fmax c maximum working frequency for data flash at given number of ws in worst conditions 8 wait states 66 mhz
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 44 3.17 ac specifications 3.17.1 pad ac specifications table 23 gives the ac electrical charact eristics at 3.3 v (3.0 v < v dd_hv_io < 3.6 v) operation. note for bcm89810 document please refer to broadcom website and download the document table 23. pad ac specification s (3.3 v, invusro[pad3v5v] = 1) pad symbol parameter load drive (pf) rise/fall 1 (ns) unit min typ max slow tswitchon propagation delay from vdd/2 of internal signal to pchannel / nchannel switch on condition 25 3 ? 40 ns 50 3 ? 40 ns 100 3 ? 40 ns 200 3 ? 40 ns tr/tf slope at rising/falling edge 25 4 ? 40 ns 50 6 ? 50 ns 100 10 ? 75 ns 200 14 ? 100 ns freq frequency of operation 25 ? ? 4 mhz 50 ? ? 2 mhz 100 ? ? 2 mhz 200 ? ? 2 mhz current slew slew rate at rising edge of current 25 0.01 ? 2 ma/ns 50 0.01 ? 2 ma/ns 100 0.01 ? 2 ma/ns 200 0.01 ? 2 ma/ns
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 45 medium tswitchon propagation delay from vdd/2 of internal signal to pchannel / nchannel switch on condition 25 1 ? 15 ns 50 1 ? 15 ns 100 1 ? 15 ns 200 1 ? 15 ns tr/tf slope at rising/falling edge 25 2 ? 12 ns 50 4 ? 25 ns 100 8 ? 40 ns 200 14 ? 70 ns freq frequency of operation 25 ? ? 40 mhz 50 ? ? 20 mhz 100 ? ? 13 mhz 200 ? ? 7 mhz current slew slew rate at rising edge of current 25 2.5 ? 7 ma/ns 50 2.5 ? 7 ma/ns 100 2.5 ? 7 ma/ns 200 2.5 ? 7 ma/ns fast tswitchon propagation delay from vdd/2 of internal signal to pchannel / nchannel switch on condition 25 1 ? 6 ns 50 1 ? 6 ns 100 1 ? 6 ns 200 1 ? 6 ns tr/tf slope at rising/falling edge 25 1 ? 4 ns 50 1.5 ? 7 ns 100 3 ? 12 ns 200 5 ? 18 ns freq frequency of operation 25 ? ? 72 mhz 50 ? ? 55 mhz 100 ? ? 40 mhz 200 ? ? 25 mhz current slew slew rate at rising edge of current 25 3 ? 40 ma/ns 50 3 ? 40 ma/ns 100 3 ? 40 ma/ns 200 3 ? 40 ma/ns table 23. pad ac specification s (3.3 v, invusro[pad3v5v] = 1) pad symbol parameter load drive (pf) rise/fall 1 (ns) unit min typ max
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 46 figure 15. pad output delay symmetric tswitchon propagation delay from vdd/2 of internal signal to pchannel / nchannel switch on condition 25 1 ? 8 ns tr/tf slope at rising/falling edge 25 1 ? 5 ns trise/tfall delay at rising/falling edge 25 3 ? 12 ns |trise - tfall delay between rising and falling edge 25 0.05 ? 1 ns freq frequency of operation 25 ? ? 50 mhz current slew slew rate at rising edge of current 25 3 ? 25 ma/ns 1 slope at rising/falling edge table 23. pad ac specification s (3.3 v, invusro[pad3v5v] = 1) pad symbol parameter load drive (pf) rise/fall 1 (ns) unit min typ max v dd_hv_io /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 47 3.18 ac timing characteristics 3.18.1 generic timing diagrams the generic timing diagrams in figure 16 and figure 17 apply to all i/o pins with pad types fast, slow and medium. see section 2.2, ?signal descriptions for the pad type for each pin. figure 16. generic output delay/hold timing figure 17. generic i nput setup/hold timing v dd_hv_iox /2 clkout a?maximum output delay time b?minimum output hold time v dd_hv_iox /2 a b i/o outputs v dd_hv_iox /2 a b clkout v dd_hv_iox /2 i/o inputs a?minimum input setup time b?minimum input hold time
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 48 3.18.2 reset_b pin characteristics the MPC5606E implements a dedicated bidirectional reset pin. figure 18. start-up reset requirements figure 19. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 49 3.18.3 nexus and jtag timing table 24. reset electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v ih sr p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol cc p output low level push pull, i ol = 3 ma, ? ? 0.1v dd v t tr cc d output transition time output pin 2 medium configuration 2 c l includes device and package capacitance (c pkg <5pf). c l = 25 pf, v dd = 3.3 v 10% ? ? 12 ns c l = 50 pf, v dd = 3.3 v 10% ??25 c l = 100 pf, v dd = 3.3 v 10% ??40 w frst sr p reset input filtered pulse ???40ns w nfrst sr p reset input not filtered pulse ?500??ns |i wpu | cc p weak pull-up current absolute value v dd = 3.3 v 10% 10 ? 150 a table 25. nexus debug port timing 1 no. symbol c parameter value unit min typ max 1t mcyc cc d mcko cycle time 2 ? 8 t cyc 2a t mcycp cc d mcko cycle period 15 ? ? ns 2b t mdc cc d mcko duty cycle 48 ? 52 % 3t mdov cc d mcko low to mdo data valid 2 ?0.1 ? 0.22 t mcyc 4t mseov cc d mcko low to mseo data valid 2 ?0.1 ? 0.22 t mcyc 5t evtov cc d mcko low to evto data valid 2 ?0.1 ? 0.22 t mcyc 6t tcyc cc d tck cycle time 50 ? ? ns 7t tdc cc d tck duty cycle 40 ? 60 %
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 50 figure 20. nexus output timing figure 21. nexus event trigger and test clock timings 8t ntdis cc d tdi data setup time 0.2 ? ? t tcyc t ntmss cc d tms data setup time 0.2 ? ? t tcyc 9t ntdih cc d tdi data hold time 0.1 ? ? t tcyc t ntmsh cc d tms data hold time 0.1 ? ? t tcyc 10 t tdov cc d tck low to tdo data valid ? ? 25 ns 11 t tdov cc d tck low to tdo data invalid 0.1 ? ? t tcyc 1 all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. 2 mdo, mseo , and evto data is held valid until next mcko low cycle. table 25. nexus debug port timing 1 (continued) no. symbol c parameter value unit min typ max 2 a 4 5 mcko mdo mseo evto output data valid 3 2b tck 6 7
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 51 figure 22. nexus tdi, tms, tdo timing 3.18.4 gpio timing the gpio specifications for setup time and output valid relative to clkout are the same for all pins on the device regardless of the primary pin function. table 26. gpio timing no. symbol characteristic min. max. unit 1t read gpio read time 5 ? t cyc 2t write gpio write time 6 ? t cyc tdo 8 9 tms, tdi 11 tck 10
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 52 3.18.5 external interrupt timing (irq pin) figure 23. external interrupt timing 3.18.6 flexcan timing 3.18.7 linflex timing minimum design target for interface frequency is 2 mbit/s. table 27. external interrupt timing 1 1 irq timing specified at f sys = 64 mhz and v dd_hv_iox = 3.0 v, t a = t l to t h , and cl = 200 pf with src = 0b00. no. symbol c parameter conditions min max unit 1t ipwl cc d irq pulse width low ? 4 ? t cyc 2t ipwh cc d irq pulse width high ? 4 ? t cyc 3t icyc cc d irq edge to edge time 2 2 applies when irq pins are configured for rising edge or falling edge events, but not both. ?4+n 3 3 n = isr time to clear the flag ?t cyc table 28. flexcan timing 1 1 flexcan timing specified at f sys = 64 mhz, vdd = 1.35 v to 1.65 v, vddeh = 3.0 v to 5.5 v, vrc33 and vddpll = 3.0 v to 3.6 v, t a = tl to th, and cl = 50 pf with src = 0b00. num characteristic symbol min. value max. value unit 1 ctnx output valid after clkout rising edge (output delay) t canov ? 26.0 ns 2 cnrx input valid to clkout rising edge (setup time) t cansu ?9.8ns irq 2 3 1
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 53 3.18.8 dspi timing table 29. dspi timing no. symbol c parameter conditions min max unit 1t sck cc d dspi cycle time master (mtfe = 0) 62.5 ? ns slave (mtfe = 0) 128 ? master (mtfe = 1,cpha=1) 31.25 ? 2t csc cc d cs to sck delay ? 16 ? ns 3t asc cc d after sck delay ? 16 ? ns 4t sdc cc d sck duty cycle ? 0.4 * t sck 0.6 * t sck ns 5t a cc d slave access time ss active to sout valid ? 40 ns 6t dis cc d slave sout disable time ss inactive to sout high-z or invalid ? 10 ns 7t pcsc cc d pcsx to pcss time ? 13 ? ns 8t pasc cc d pcss to pcsx time ? 13 ? ns 9t sui cc d data setup time for inputs master (mtfe = 0) 12 ? ns slave 2? master (mtfe = 1, cpha = 0) na 1 1 this mode is not feasible at 32 mhz. master (mtfe = 1, cpha = 1) 12 ? 10 t hi cc d data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) na 1 master (mtfe = 1, cpha = 1) ?5 ? 11 t suo cc d data valid (after sck edge) master (mtfe = 0) ? 4 ns slave ? 33 master (mtfe = 1, cpha = 0) na 1 master (mtfe = 1, cpha = 1) ? 11 12 t ho cc d data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6 ? master (mtfe = 1, cpha = 0) na 1 master (mtfe = 1, cpha = 1) ?2 ?
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 54 figure 24. dspi classic spi timing ? master, cpha = 0 figure 25. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1)
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 55 figure 26. dspi classic spi timing ? slave, cpha = 0 figure 27. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 56 figure 28. dspi modified transfer format timing ? master, cpha = 0 figure 29. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 57 figure 30. dspi modified transfer format timing ? slave, cpha = 0 figure 31. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 58 figure 32. dspi pcs strobe (pcss ) timing 3.18.9 video interface timing table 30 details the MPC5606E?s video encoder block?s pixel input clocking requirement. figure 33. video interface timing table 30. input pixel clock characteristics no. parameter min max unit 1 pdi clock period 10 ? ns 2 pdi clock duty cycle 50 50 % 3 input setup time 2 ? ns 4 input hold time 2 ? ns 5 input pixel clock slew rate ? 2 ns pcsx 7 8 pcss vclkin 3 4 vid_data[15:0] input data valid vid_line_v vid_frame_v 1
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 59 3.18.10 fast ethernet interface mii signals use cmos signal levels compatible with devices oper ating at either 5.0 v or 3.3 v. signals are not ttl compatible. they follow the cmos elec trical characteristics. 3.18.10.1 mii receive signal timing (r xd[3:0], rx_dv, rx_er, and rx_clk) the receiver functions correctly up to a rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, the sy stem clock frequency must exceed four times the rx_clk frequency. figure 34. mii receive signal timing diagram 3.18.10.2 mii transmit signal timing (txd[3:0], tx_en, tx_er, tx_clk) the transmitter functions correctly up to a tx_clk maximu m frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the sy stem clock frequency must exceed four times the tx_clk frequency. the transmit outputs (txd[3:0], tx_en, tx_er) can be programme d to transition from either the rising or falling edge of tx_clk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for details of this option and how to enable it. table 31. mii receive signal timing no. parameter min max unit 1 rx clock period 40 ? ns 2 rxd[3:0], rx_dv, rx_er to rx_clk setup 5? ns 3 rx_clk to rxd[3:0], rx_dv, rx_er hold 5? ns 4 rx clock duty cycle 40 60 % table 32. mii transmit signal timing 1 1 output pads configured with src = 0b11. no. parameter min max unit 5 tx clock period 40 ? ns 6 tx_clk to txd[3:0], tx_en, tx_er invalid 5? ns 7 tx_clk to txd[3:0], tx_en, tx_er valid ?25 ns 8 tx clock duty cycle 40 60 % 2 3 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er 4 1
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 60 figure 35. mii transmit signal timing diagram 3.18.10.3 mii async inputs signal timing (crs and col) figure 36. mii async inputs timing diagram 3.18.10.4 mii serial management channel timing (mdio and mdc) the fec functions correctly with a maximum mdc frequency of 5 mhz. table 33. mii async inputs signal timing 1 1 output pads configured with src = 0b11. no. parameter min max unit 9 crs, col minimum pulse width 1.5 ? tx_clk period table 34. mii serial management channel timing (mdio and mdc) no. parameter min max unit 1 mdio input delay setup 28 ? ns 2 mdio input delay hold 0? ns 3 mdio output delay valid ?25 ns 4 mdio output delay invalid 0? ns 5 mdc clock period 100 ? ns 6 mdc duty cycle 40 60 % 7 tx_clk (input) txd[3:0] (outputs) tx_en tx_er 6 crs, col 9
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 61 3.18.11 i 2 c timing table 35. i 2 c scl and sda input timing specifications no. symbol parameter value unit min max 1 ? d start condition ho ld time 2 ? ip bus cycle 1 1 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. it is equal to the system clock (sys_clk). 2 ? d clock low time 8 ? ip bus cycle 1 4 ? d data hold time 0.0 ? ns 6 ? d clock high time 4 ? ip bus cycle 1 7 ? d data setup time 0.0 ? ns 8 ? d start condition setup time (for re peated start condition only) 2 ? ip bus cycle 1 9 ? d stop condition setup time 2 ? ip bus cycle 1 table 37. i 2 c scl and sda output timing specifications no. symbol parameter value unit min max 1 1 1 programming ibfd (i 2 c bus frequency divider) with the maximum frequency results in the minimum output timings listed. the i 2 c interface is designed to scale the data transition time, moving it to the middle of the scl low period. the actual position is affected by the presca le and division values programmed in ifdr. ? d start condition hold time 6 ? ip bus cycle 2 2 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. 2 1 ? d clock low time 10 ? ip bus cycle 1 3 3 3 because scl and sda are open-drain-type outputs, which the processor can only actively drive low, the time scl or sda takes to reach a high level depends on external signal capacitance and pull-up resistor values. ? d scl/sda rise time ? 99.6 ns 4 1 ? d data hold time 7 ? ip bus cycle 1 5 1 ? d scl/sda fall time ? 99.5 ns 6 1 ? d clock high time 10 ? ip bus cycle 1 7 1 ? d data setup time 2 ? ip bus cycle 1 8 1 ? d start condition setup time (for repeated start condition only) 20 ? ip bus cycle 1 9 1 ? d stop condition setup time 10 ? ip bus cycle 1
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 62 figure 38. i 2 c input/output timing 3.18.12 sai timing all timing requirements are specified rela tive to the clock period or to the minimum allowed clock period of a device. table 36. master mode sai timing no. parameter value unit min max operating voltage 2.7 3.6 v s1 sai_mclk cycle time 40 ? ns s2 sai_mclk pulse width high/low 45% 55% mclk period s3 sai_bclk cycle time 80 ? bclk period s4 sai_bclk pulse width high/low 45% 55% ns s5 sai_bclk to sai_fs output valid ? 15 ns s6 sai_bclk to sai_fs output invalid 0 ? ns s7 sai_bclk to sai_txd valid ? 15 ns s8 sai_bclk to sai_txd invalid 0 ? ns s9 sai_rxd/sai_fs input setup before sai_bclk 28 ? ns s10 sai_rxd/sai_fs input hold after sai_bclk 0 ? ns scl sda 1 2 3 4 5 6 7 8 9
electrical characteristics MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 63 figure 39. sai timing master modes table 37. slave mode sai timing no. parameter value unit min max operating voltage 2.7 3.6 v s11 sai_bclk cycle time (input) 80 ? ns s12 sai_bclk pulse width high/low (input) 45% 55% bclk period s13 sai_fs inpu t setup before sai_bclk 10 ? ns s14 sai_fs input hold after sai_bclk 2 ? ns s15 sai_bclk to sai_txd/ sai_fs output valid ? 28 ns s16 sai_bclk to sai_txd/sai _fs output invalid 0 ? ns s17 sai_rxd setup before sai_bclk 10 ? ns s18 sai_rxd hold af ter sai_bclk 2 ? ns
MPC5606E microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 64 figure 40. sai timing slave modes
package mechanical data MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 65 4 package mechanical data 4.1 121 mapbga mechanical outline drawing figure 41. 121 mapbga package mechanical drawing (part 1)
MPC5606E microcontroller data sheet, rev. 3 package mechanical data freescale semiconductor 66 figure 42. 121 mapbga package mechanical drawing (part 2)
revision history of this document MPC5606E microcontroller data sheet, rev. 3 freescale semiconductor 67 appendix a revision history of this document this appendix describes corrections to the MPC5606E microc ontroller data sheet. for conv enience, the corrections are grouped by revision. grammatical and formatting changes are not listed here unless the meaning of something changed. note this revision history uses clickable cross-re ferences for ease of navigation.the numbers and titles in each cross-reference are re lative to the latest published release. table a-1. revision history topic description revision 1 section 3.3, absolute maximum ratings in table 4 (absolute maximum ratings) , updated junction temperature under bias temprature from 150c to 132c section 3.4, recommended operating conditions in table 5 (recommended operating conditions) , updated junction temperature under bias temprature from 150c to 132c revision 2 section 2.2, signal descriptions in ta bl e 4 updated the ports b[4], b[13 ], b[14], b[15], c[0] an d c[1] from gpio to gpi section 3.15, temperature sensor electrical characteristics in ta bl e 1 9 updated the temperature monitoring range from 150c to 132c
MPC5606E microcontroller data sheet, rev. 3 revision history of this document freescale semiconductor 68
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